The present invention relates to the fabrication of integrated circuits. More particularly, the invention provides a technique, including a method and apparatus, for reducing the surface sensitivity of a sub-atmospheric chemical vapor deposition (herein SACVD) deposited silicon oxide (also referred to as SACVD undoped silicon glass (USG)) film utilized in the manufacture of integrated circuits.
One of the primary steps in the fabrication of modern semiconductor devices is the formation of a thin film on a semiconductor substrate by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition, or "CVD." Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CVD processes operate can damage device structures having metal layers.
One particular thermal CVD process that has been developed to deposit insulation films over metal layers at relatively low, nondamaging temperatures includes deposition of a silicon oxide layer from tetraethylorthosilane (herein TEOS) and ozone precursor gases. Such a TEOS/ozone silicon oxide film may be deposited under carefully controlled pressure conditions in the range of between about 100-700 torr, and is therefore commonly referred to as a subatmospheric CVD (SACVD) film. The high reactivity of TEOS with ozone reduces the external energy required for a chemical reaction to take place, and thus lowers the required temperature for such SACVD processes.
Another CVD method of depositing silicon oxide layers over metal layers at relatively low temperatures includes plasma-enhanced CVD (herein PECVD) techniques. Plasma-enhanced CVD techniques promote excitation and/or disassociation of the reactant gases by the application of radio frequency (RF) energy to a reaction zone proximate the substrate surface, thereby creating a plasma of highly reactive species. The high reactivity of the released species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such PECVD processes.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two-year/half-size rule (often called "Moore's Law"), which means that the number of devices which will fit on a chip doubles every two years. Today's wafer fabrication plants are routinely producing 0.5 and even 0.35 micron feature size devices, and tomorrow's plants soon will be producing devices having even smaller geometries.
As device sizes become smaller and integration density increases, one issue that has become increasingly important is the capability of a deposited insulating silicon oxide layer to fill closely spaced gaps (referred to as a film's "gap fill" capability) such as those between adjacent metal lines.
The properties of the SACVD layer depend strongly on the underlying surface onto which it is deposited. When the SACVD layer is deposited over a silicon oxide layer, such as the steam oxide or PECVD lining layer, or on the surface of a metal, the quality of the SACVD layer generally deteriorates because of surface sensitivity to the underlying layer. The quality of a CVD silicon oxide layer is not as good as the quality of "steam oxide" grown on the surface of a silicon substrate by heating the substrate in the presence of steam. The surface sensitivity of the SACVD layer is manifested by an increase in the wet etch rate compared to the wet etch rate of thermally grown steam oxide, and by a decrease in the deposition rate and a rougher surface morphology as compared to the deposition rate and surface morphology of an SACVD layer deposited directly on a silicon substrate.
The wet etch rate ratio (herein WERR) is the ratio of the wet etch rate of an SACVD layer deposited over the PECVD lining layer to the wet etch rate of a thermally grown steam oxide. The CVD layer is typically more porous than a steam layer and tends to etch away more quickly than the steam oxide. The deposition rate ratio (DRR) is the ratio of the deposition rate of the SACVD layer deposited over the PECVD lining layer to the deposition rate of an SACVD layer deposited directly on a bare silicon substrate. Thus, surface sensitivity is manifested by a high WERR and a low DRR. Surface sensitivity is also referred to as the "base layer effect" because the deterioration of quality of the SACVD layer depends on the properties of the base layer over which it is deposited.
One process that has been used successfully to fill gaps up to an aspect ratio of 2.0 or higher and reduce the surface sensitivity of an SACVD layer is the deposition of a two-layer silicon oxide dielectric film. First, a thin PECVD silicon oxide layer ("the PECVD lining layer") is deposited over stepped topography (such as adjacent metal lines) of a substrate. Second, an SACVD TEOS/ozone silicon oxide layer ("the SACVD layer") is deposited. The PECVD lining layer functions as an initial lining layer and diffusion barrier for the overlying SACVD layer. The lining layer is typically of lower quality than the SACVD layer, but its presence lowers the surface sensitivity of the overlying SACVD layer that fills in the gaps between the metal lines. The entire deposition sequence takes place in an in situ process.
Various techniques have been utilized to reduce the sensitivity of the SACVD layer of a two-layer silicon oxide gap-filling film. One method, developed at Applied Materials, Inc., is to treat the PECVD lining layer with an N.sub.2 plasma, excited by mixed RF frequencies (13.56 MHz and 350 KHz), at a relatively high pressure (.gtoreq.1.5 torr) prior to deposition of the SACVD layer.
Another technique utilized to reduce the surface sensitivity of an SACVD silicon oxide layer is to deposit the layer over a lining silicon oxide layer formed using TEOS and ozone as process gases at low pressure and high ozone concentration.